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DFT Tips for implementing Boundary Scan in your design.
Boundary Scan is an extremely powerful test tool, but a lot of people in the test industry have been
pressing only for on-board testing via Boundary Scan. Products like the AccessExtender(TM) can easily
add to your test coverage in several ways;
- With a simple adapter (your UUT board connector to a 2x25 100mil connector) designed into the white
space(unused) on your products PWB panel, every time a board is built you get an adapter for
free(practically). These adapters then become disposable Production usable pieces of your test setup.
Interfacing the AccessExtender(TM) to your product then becomes easy .... and the AccessExtender(TM)
is re-usable for testing multiple products.
- Today's Boundary Scan Software has acquired the complexity and intelligence of a pseudo In-Circuit
tester. With the supportive 'glue-logic' models defining the non-scan components on your board under
test, today's Boundary Scan Software has the ability to propagate faults through 'glue-logic'. The only
thing missing is boundary scan access to the connector inputs and outputs of the 'glue-logic' and/or on
and off your board. With the AccessExtender(TM) as external pseudo test points integrated into your
Boundary Scan Software, Boundary Scan test vectors are automatically generated through your boards
connectors.
- Many people today are combining Boundary Scan testing with In-Circuit testing. They are doing this
because of high node count designs and test point limitations on existent installed ICT test capital. By
integrating the AccessExtender(TM) into your bed-of-nails fixture, you acquire immediate boundary scan
test points. And, if you are using a wireless fixture, by designing in a 2x25 100 mil connector to interface
to the AccessExtender(TM) you eliminate a bundle of wire wrap wires.
- Older DFT techniques, such as NAND Trees, can now be tested by providing full Boundary Scan
access to your NAND Tree chip via a bed-of-nails and the AccessExtender(TM). This will allow you to
write NAND Tree tests, increasing your product's test coverage via Boundary Scan.
- Loopback testing is a popular Boundary Scan test recommendation. Looping a scannable connector
on itself can increase your test coverage, but has limitations on fault detection, diagnosis and actually
induces false shorts that cannot be detected on UUT. Adding in an AccessExtender(TM) instead of a
loopback, can add coverage and provide full signal directional fault isolation. You can also add
additional Boundary Scan pins from the AccessExtender(TM) to 2 point networks, allowing for 3 point
fault isolation, as opposed to 2 point (point to point) isolation where you can not identify the open
pin....this will help eliminate finger pointing between you, your ODM/CM and/or semiconductor
manufacturer when faults occur.
- A lot of designers want to control transceivers on a board with soft-terminating pullups and pulldowns
on the Output Enable(OE) and Direction(DIR) pins. If your designer were to provide
you with an additional boundary scan controllable signals (say from a spare pin on an FPGA) to these
OE and DIR lines, test coverage and fault class coverage could be increased on all scannable lines
going to/from the transceiver.
pressing only for on-board testing via Boundary Scan. Products like the AccessExtender(TM) can easily
add to your test coverage in several ways;
- With a simple adapter (your UUT board connector to a 2x25 100mil connector) designed into the white
space(unused) on your products PWB panel, every time a board is built you get an adapter for
free(practically). These adapters then become disposable Production usable pieces of your test setup.
Interfacing the AccessExtender(TM) to your product then becomes easy .... and the AccessExtender(TM)
is re-usable for testing multiple products.
- Today's Boundary Scan Software has acquired the complexity and intelligence of a pseudo In-Circuit
tester. With the supportive 'glue-logic' models defining the non-scan components on your board under
test, today's Boundary Scan Software has the ability to propagate faults through 'glue-logic'. The only
thing missing is boundary scan access to the connector inputs and outputs of the 'glue-logic' and/or on
and off your board. With the AccessExtender(TM) as external pseudo test points integrated into your
Boundary Scan Software, Boundary Scan test vectors are automatically generated through your boards
connectors.
- Many people today are combining Boundary Scan testing with In-Circuit testing. They are doing this
because of high node count designs and test point limitations on existent installed ICT test capital. By
integrating the AccessExtender(TM) into your bed-of-nails fixture, you acquire immediate boundary scan
test points. And, if you are using a wireless fixture, by designing in a 2x25 100 mil connector to interface
to the AccessExtender(TM) you eliminate a bundle of wire wrap wires.
- Older DFT techniques, such as NAND Trees, can now be tested by providing full Boundary Scan
access to your NAND Tree chip via a bed-of-nails and the AccessExtender(TM). This will allow you to
write NAND Tree tests, increasing your product's test coverage via Boundary Scan.
- Loopback testing is a popular Boundary Scan test recommendation. Looping a scannable connector
on itself can increase your test coverage, but has limitations on fault detection, diagnosis and actually
induces false shorts that cannot be detected on UUT. Adding in an AccessExtender(TM) instead of a
loopback, can add coverage and provide full signal directional fault isolation. You can also add
additional Boundary Scan pins from the AccessExtender(TM) to 2 point networks, allowing for 3 point
fault isolation, as opposed to 2 point (point to point) isolation where you can not identify the open
pin....this will help eliminate finger pointing between you, your ODM/CM and/or semiconductor
manufacturer when faults occur.
- A lot of designers want to control transceivers on a board with soft-terminating pullups and pulldowns
on the Output Enable(OE) and Direction(DIR) pins. If your designer were to provide
you with an additional boundary scan controllable signals (say from a spare pin on an FPGA) to these
OE and DIR lines, test coverage and fault class coverage could be increased on all scannable lines
going to/from the transceiver.
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DFT Tips - Test Coverage Improvement