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DFT Tips for implementing Boundary Scan in your design.
1) Simple rule - provide Boundary Scan access to all memory device pins. Simple to ask for, but very
difficult to get. The reason for this is that most memory test models are typically coded for the stand-alone
part. If you have topological restrictions induced due to non-access, more than likely the model will not
work and you will have to modify or code a new memory test algorithm for your parts. This can require
considerable effort, given the device complexity.
2) Memory Clocks - if clock distribution chips are used and they have an internal PLL, try to use one that
allows a static test clock input to be propagated to the output. This will allow bypassing the PLL or any
locked in frequency ranges(scan runs slow compared to the system clock). Designers are concerned
about signal integrity, especially on CLKs. If a bypass input is provided into the clock distribution chip, a
static clock can be driven by an unused pin(scan cell). This will remove any discussion about CLK signal
integrity with your designer; yet still provide you indirect access to the Memory device CLKs from Scan.
3) Simple rule - provide Boundary Scan access to all memory device pins. Simple to ask for, but very
difficult to get. We repeat this because it is so, so important. Synchronous memory devices are
synchronous to their input CLKs. If you cannot control their CLKs, first off - you may not be able to test the
memory part, BUT more importantly, you may induce a back-drive problem if you try to test them anyways.
Parallel Boundary Scan testing runs slow (roughly TCK rate / #cells). In Command/NoOp/Data type of
operations (which most synchronous memory parts use) if you do not have access to stop the CLK, by the
time you get to remove your stimulus input data, the part may have already burst-ed out it's stored
data(aka : bus turn-around)...causing a back-drive problem. Simple rule - provide Boundary Scan access
to all memory device pins.
4) Use spare scan cells/spare pins to provide access to the memory parts. We like to recommend using
spare FPGA pins/scan cells to provide this access...if of course, you have spare pins...
5) Some people feel that on synchronous memory devices, the Bank Address Select lines should be
tested as a normal address lines. Meaning, that these BA bits should be toggled during Boundary Scan
memory testing, just like a normal address line. We are not going to say that this is entirely incorrect, nor
are we going to say that this is entirely correct. We recommend you check your datasheet on these
devices to understand if a pre-charge and/or auto-refresh cycles (or other cycles) need to be initiated
PRIOR to changing Bank Address select lines. It has been our experience that treating these BA bits as
regular address bits will merely produce intermittent failures on a lot of devices. We recommend either a
custom coded memory test model, or treat the BA bits as statically set bits for the entire test. Yes, static
setting will cause you to loose coverage....but how long will a Production Manager put up with an
intermittent test on his line?
6) Also be aware, that the IEEE has a Working Group specifically targeted at memory DFT. This is the
P1581 Working group. You can review the White Paper regarding P1581 by clicking on the following link,
P1581 Description White Paper.
difficult to get. The reason for this is that most memory test models are typically coded for the stand-alone
part. If you have topological restrictions induced due to non-access, more than likely the model will not
work and you will have to modify or code a new memory test algorithm for your parts. This can require
considerable effort, given the device complexity.
2) Memory Clocks - if clock distribution chips are used and they have an internal PLL, try to use one that
allows a static test clock input to be propagated to the output. This will allow bypassing the PLL or any
locked in frequency ranges(scan runs slow compared to the system clock). Designers are concerned
about signal integrity, especially on CLKs. If a bypass input is provided into the clock distribution chip, a
static clock can be driven by an unused pin(scan cell). This will remove any discussion about CLK signal
integrity with your designer; yet still provide you indirect access to the Memory device CLKs from Scan.
3) Simple rule - provide Boundary Scan access to all memory device pins. Simple to ask for, but very
difficult to get. We repeat this because it is so, so important. Synchronous memory devices are
synchronous to their input CLKs. If you cannot control their CLKs, first off - you may not be able to test the
memory part, BUT more importantly, you may induce a back-drive problem if you try to test them anyways.
Parallel Boundary Scan testing runs slow (roughly TCK rate / #cells). In Command/NoOp/Data type of
operations (which most synchronous memory parts use) if you do not have access to stop the CLK, by the
time you get to remove your stimulus input data, the part may have already burst-ed out it's stored
data(aka : bus turn-around)...causing a back-drive problem. Simple rule - provide Boundary Scan access
to all memory device pins.
4) Use spare scan cells/spare pins to provide access to the memory parts. We like to recommend using
spare FPGA pins/scan cells to provide this access...if of course, you have spare pins...
5) Some people feel that on synchronous memory devices, the Bank Address Select lines should be
tested as a normal address lines. Meaning, that these BA bits should be toggled during Boundary Scan
memory testing, just like a normal address line. We are not going to say that this is entirely incorrect, nor
are we going to say that this is entirely correct. We recommend you check your datasheet on these
devices to understand if a pre-charge and/or auto-refresh cycles (or other cycles) need to be initiated
PRIOR to changing Bank Address select lines. It has been our experience that treating these BA bits as
regular address bits will merely produce intermittent failures on a lot of devices. We recommend either a
custom coded memory test model, or treat the BA bits as statically set bits for the entire test. Yes, static
setting will cause you to loose coverage....but how long will a Production Manager put up with an
intermittent test on his line?
6) Also be aware, that the IEEE has a Working Group specifically targeted at memory DFT. This is the
P1581 Working group. You can review the White Paper regarding P1581 by clicking on the following link,
P1581 Description White Paper.
DFT Tips - Memory testing
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