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DFT Tips for implementing Boundary Scan in your design.
1) Asynchronous Resets - Take care - Asynchronous resets on your board MAY reset the Boundary Scan
during testing. This will cause huge problems during test vector debug. Talk to your designer about
asynchronous resets and ensure they do not tie System Reset to TRST. If they do, make sure you hold
this signal de-asserted during vector application. Talk to your Boundary Scan Software provider about
how to add in constraints or disabling HOLD conditions.
2) Resets - Normally, non-asynchronous resets on your board should not affect Boundary Scan. We
recommend you check your chip spec's for more information on how chips are reset.
3) Clocks - Tested for the 'presence' of system clocks via Boundary Scan. Sensing that a clock is
present and running high and low, is extremely easy if testing within a loop.
4) Clock distribution chips - Boundary Scan access is needed to both the + and - CLK signals going to
synchronous memories....BUT designers are worried about skew on these clocks. We recommend
using clock distribution chips that allow for a secondary clock input (test input) to be applied, which
bypasses any internal PLL's. This will allow for a static clock input that can be driven by Boundary Scan.
This will keep your designers concerns about clock skew out of the conversation. Contact us for more
details on some chips that we recommend.
5) System reset and Flash reset - Although this may be a necessary issue for your designer, we
recommend separating system reset from any Flash device reset. A small issue comes up (which may
only be a software model change for scan testing) in that most Flash models will toggle reset to initialize
the Flash device for testing or programming. If Flash reset is toggled, so is system reset and this may
reset your Boundary Scan chain at the same time...taking the tester Software provider about how to add
in constraints or HOLD conditions to avoid this issue.
during testing. This will cause huge problems during test vector debug. Talk to your designer about
asynchronous resets and ensure they do not tie System Reset to TRST. If they do, make sure you hold
this signal de-asserted during vector application. Talk to your Boundary Scan Software provider about
how to add in constraints or disabling HOLD conditions.
2) Resets - Normally, non-asynchronous resets on your board should not affect Boundary Scan. We
recommend you check your chip spec's for more information on how chips are reset.
3) Clocks - Tested for the 'presence' of system clocks via Boundary Scan. Sensing that a clock is
present and running high and low, is extremely easy if testing within a loop.
4) Clock distribution chips - Boundary Scan access is needed to both the + and - CLK signals going to
synchronous memories....BUT designers are worried about skew on these clocks. We recommend
using clock distribution chips that allow for a secondary clock input (test input) to be applied, which
bypasses any internal PLL's. This will allow for a static clock input that can be driven by Boundary Scan.
This will keep your designers concerns about clock skew out of the conversation. Contact us for more
details on some chips that we recommend.
5) System reset and Flash reset - Although this may be a necessary issue for your designer, we
recommend separating system reset from any Flash device reset. A small issue comes up (which may
only be a software model change for scan testing) in that most Flash models will toggle reset to initialize
the Flash device for testing or programming. If Flash reset is toggled, so is system reset and this may
reset your Boundary Scan chain at the same time...taking the tester Software provider about how to add
in constraints or HOLD conditions to avoid this issue.
DFT Tips - Clocks and Resets
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